
prime-number-c-vs-c++:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004008f0 <_init>:
  4008f0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4008f4:	910003fd 	mov	x29, sp
  4008f8:	94000060 	bl	400a78 <call_weak_fn>
  4008fc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400900:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400910 <.plt>:
  400910:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400914:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xf7e8>
  400918:	f947fe11 	ldr	x17, [x16, #4088]
  40091c:	913fe210 	add	x16, x16, #0xff8
  400920:	d61f0220 	br	x17
  400924:	d503201f 	nop
  400928:	d503201f 	nop
  40092c:	d503201f 	nop

0000000000400930 <free@plt>:
  400930:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400934:	f9400211 	ldr	x17, [x16]
  400938:	91000210 	add	x16, x16, #0x0
  40093c:	d61f0220 	br	x17

0000000000400940 <memset@plt>:
  400940:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400944:	f9400611 	ldr	x17, [x16, #8]
  400948:	91002210 	add	x16, x16, #0x8
  40094c:	d61f0220 	br	x17

0000000000400950 <__libc_start_main@plt>:
  400950:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400954:	f9400a11 	ldr	x17, [x16, #16]
  400958:	91004210 	add	x16, x16, #0x10
  40095c:	d61f0220 	br	x17

0000000000400960 <clock@plt>:
  400960:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400964:	f9400e11 	ldr	x17, [x16, #24]
  400968:	91006210 	add	x16, x16, #0x18
  40096c:	d61f0220 	br	x17

0000000000400970 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>:
  400970:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400974:	f9401211 	ldr	x17, [x16, #32]
  400978:	91008210 	add	x16, x16, #0x20
  40097c:	d61f0220 	br	x17

0000000000400980 <_Znwm@plt>:
  400980:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400984:	f9401611 	ldr	x17, [x16, #40]
  400988:	9100a210 	add	x16, x16, #0x28
  40098c:	d61f0220 	br	x17

0000000000400990 <__cxa_atexit@plt>:
  400990:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400994:	f9401a11 	ldr	x17, [x16, #48]
  400998:	9100c210 	add	x16, x16, #0x30
  40099c:	d61f0220 	br	x17

00000000004009a0 <_ZdaPv@plt>:
  4009a0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009a4:	f9401e11 	ldr	x17, [x16, #56]
  4009a8:	9100e210 	add	x16, x16, #0x38
  4009ac:	d61f0220 	br	x17

00000000004009b0 <_ZSt24__throw_out_of_range_fmtPKcz@plt>:
  4009b0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009b4:	f9402211 	ldr	x17, [x16, #64]
  4009b8:	91010210 	add	x16, x16, #0x40
  4009bc:	d61f0220 	br	x17

00000000004009c0 <_ZNSt8ios_base4InitC1Ev@plt>:
  4009c0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009c4:	f9402611 	ldr	x17, [x16, #72]
  4009c8:	91012210 	add	x16, x16, #0x48
  4009cc:	d61f0220 	br	x17

00000000004009d0 <malloc@plt>:
  4009d0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009d4:	f9402a11 	ldr	x17, [x16, #80]
  4009d8:	91014210 	add	x16, x16, #0x50
  4009dc:	d61f0220 	br	x17

00000000004009e0 <abort@plt>:
  4009e0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009e4:	f9402e11 	ldr	x17, [x16, #88]
  4009e8:	91016210 	add	x16, x16, #0x58
  4009ec:	d61f0220 	br	x17

00000000004009f0 <_ZNSolsEi@plt>:
  4009f0:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  4009f4:	f9403211 	ldr	x17, [x16, #96]
  4009f8:	91018210 	add	x16, x16, #0x60
  4009fc:	d61f0220 	br	x17

0000000000400a00 <_ZNSolsEl@plt>:
  400a00:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400a04:	f9403611 	ldr	x17, [x16, #104]
  400a08:	9101a210 	add	x16, x16, #0x68
  400a0c:	d61f0220 	br	x17

0000000000400a10 <__gmon_start__@plt>:
  400a10:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400a14:	f9403a11 	ldr	x17, [x16, #112]
  400a18:	9101c210 	add	x16, x16, #0x70
  400a1c:	d61f0220 	br	x17

0000000000400a20 <_ZNSt8ios_base4InitD1Ev@plt>:
  400a20:	d0000090 	adrp	x16, 412000 <free@GLIBC_2.17>
  400a24:	f9403e11 	ldr	x17, [x16, #120]
  400a28:	9101e210 	add	x16, x16, #0x78
  400a2c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400a30 <_start>:
  400a30:	d280001d 	mov	x29, #0x0                   	// #0
  400a34:	d280001e 	mov	x30, #0x0                   	// #0
  400a38:	aa0003e5 	mov	x5, x0
  400a3c:	f94003e1 	ldr	x1, [sp]
  400a40:	910023e2 	add	x2, sp, #0x8
  400a44:	910003e6 	mov	x6, sp
  400a48:	580000c0 	ldr	x0, 400a60 <_start+0x30>
  400a4c:	580000e3 	ldr	x3, 400a68 <_start+0x38>
  400a50:	58000104 	ldr	x4, 400a70 <_start+0x40>
  400a54:	97ffffbf 	bl	400950 <__libc_start_main@plt>
  400a58:	97ffffe2 	bl	4009e0 <abort@plt>
  400a5c:	00000000 	.inst	0x00000000 ; undefined
  400a60:	00400b2c 	.word	0x00400b2c
  400a64:	00000000 	.word	0x00000000
  400a68:	004012f8 	.word	0x004012f8
  400a6c:	00000000 	.word	0x00000000
  400a70:	00401378 	.word	0x00401378
  400a74:	00000000 	.word	0x00000000

0000000000400a78 <call_weak_fn>:
  400a78:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xf7e8>
  400a7c:	f947f000 	ldr	x0, [x0, #4064]
  400a80:	b4000040 	cbz	x0, 400a88 <call_weak_fn+0x10>
  400a84:	17ffffe3 	b	400a10 <__gmon_start__@plt>
  400a88:	d65f03c0 	ret
  400a8c:	00000000 	.inst	0x00000000 ; undefined

0000000000400a90 <deregister_tm_clones>:
  400a90:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400a94:	91024000 	add	x0, x0, #0x90
  400a98:	d0000081 	adrp	x1, 412000 <free@GLIBC_2.17>
  400a9c:	91024021 	add	x1, x1, #0x90
  400aa0:	eb00003f 	cmp	x1, x0
  400aa4:	540000a0 	b.eq	400ab8 <deregister_tm_clones+0x28>  // b.none
  400aa8:	b0000001 	adrp	x1, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400aac:	f941cc21 	ldr	x1, [x1, #920]
  400ab0:	b4000041 	cbz	x1, 400ab8 <deregister_tm_clones+0x28>
  400ab4:	d61f0020 	br	x1
  400ab8:	d65f03c0 	ret
  400abc:	d503201f 	nop

0000000000400ac0 <register_tm_clones>:
  400ac0:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400ac4:	91024000 	add	x0, x0, #0x90
  400ac8:	d0000081 	adrp	x1, 412000 <free@GLIBC_2.17>
  400acc:	91024021 	add	x1, x1, #0x90
  400ad0:	cb000021 	sub	x1, x1, x0
  400ad4:	9343fc21 	asr	x1, x1, #3
  400ad8:	8b41fc21 	add	x1, x1, x1, lsr #63
  400adc:	9341fc21 	asr	x1, x1, #1
  400ae0:	b40000a1 	cbz	x1, 400af4 <register_tm_clones+0x34>
  400ae4:	b0000002 	adrp	x2, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400ae8:	f941d042 	ldr	x2, [x2, #928]
  400aec:	b4000042 	cbz	x2, 400af4 <register_tm_clones+0x34>
  400af0:	d61f0040 	br	x2
  400af4:	d65f03c0 	ret

0000000000400af8 <__do_global_dtors_aux>:
  400af8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400afc:	910003fd 	mov	x29, sp
  400b00:	f9000bf3 	str	x19, [sp, #16]
  400b04:	d0000093 	adrp	x19, 412000 <free@GLIBC_2.17>
  400b08:	39468260 	ldrb	w0, [x19, #416]
  400b0c:	35000080 	cbnz	w0, 400b1c <__do_global_dtors_aux+0x24>
  400b10:	97ffffe0 	bl	400a90 <deregister_tm_clones>
  400b14:	52800020 	mov	w0, #0x1                   	// #1
  400b18:	39068260 	strb	w0, [x19, #416]
  400b1c:	f9400bf3 	ldr	x19, [sp, #16]
  400b20:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b24:	d65f03c0 	ret

0000000000400b28 <frame_dummy>:
  400b28:	17ffffe6 	b	400ac0 <register_tm_clones>

0000000000400b2c <main>:
  400b2c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400b30:	910003fd 	mov	x29, sp
  400b34:	f9000bf3 	str	x19, [sp, #16]
  400b38:	97ffff8a 	bl	400960 <clock@plt>
  400b3c:	f90017a0 	str	x0, [x29, #40]
  400b40:	94000085 	bl	400d54 <_Z5sievev>
  400b44:	2a0003e1 	mov	w1, w0
  400b48:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400b4c:	91024000 	add	x0, x0, #0x90
  400b50:	97ffffa8 	bl	4009f0 <_ZNSolsEi@plt>
  400b54:	b0000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400b58:	910ec001 	add	x1, x0, #0x3b0
  400b5c:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400b60:	91024000 	add	x0, x0, #0x90
  400b64:	97ffff83 	bl	400970 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>
  400b68:	aa0003f3 	mov	x19, x0
  400b6c:	97ffff7d 	bl	400960 <clock@plt>
  400b70:	aa0003e1 	mov	x1, x0
  400b74:	f94017a0 	ldr	x0, [x29, #40]
  400b78:	cb000020 	sub	x0, x1, x0
  400b7c:	aa0003e1 	mov	x1, x0
  400b80:	aa1303e0 	mov	x0, x19
  400b84:	97ffff9f 	bl	400a00 <_ZNSolsEl@plt>
  400b88:	aa0003e2 	mov	x2, x0
  400b8c:	b0000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400b90:	910ee000 	add	x0, x0, #0x3b8
  400b94:	aa0003e1 	mov	x1, x0
  400b98:	aa0203e0 	mov	x0, x2
  400b9c:	97ffff75 	bl	400970 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>
  400ba0:	97ffff70 	bl	400960 <clock@plt>
  400ba4:	f90017a0 	str	x0, [x29, #40]
  400ba8:	9400001c 	bl	400c18 <_Z9sieve_stlv>
  400bac:	2a0003e1 	mov	w1, w0
  400bb0:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400bb4:	91024000 	add	x0, x0, #0x90
  400bb8:	97ffff8e 	bl	4009f0 <_ZNSolsEi@plt>
  400bbc:	b0000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400bc0:	910ec001 	add	x1, x0, #0x3b0
  400bc4:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400bc8:	91024000 	add	x0, x0, #0x90
  400bcc:	97ffff69 	bl	400970 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>
  400bd0:	aa0003f3 	mov	x19, x0
  400bd4:	97ffff63 	bl	400960 <clock@plt>
  400bd8:	aa0003e1 	mov	x1, x0
  400bdc:	f94017a0 	ldr	x0, [x29, #40]
  400be0:	cb000020 	sub	x0, x1, x0
  400be4:	aa0003e1 	mov	x1, x0
  400be8:	aa1303e0 	mov	x0, x19
  400bec:	97ffff85 	bl	400a00 <_ZNSolsEl@plt>
  400bf0:	aa0003e2 	mov	x2, x0
  400bf4:	b0000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  400bf8:	910ee000 	add	x0, x0, #0x3b8
  400bfc:	aa0003e1 	mov	x1, x0
  400c00:	aa0203e0 	mov	x0, x2
  400c04:	97ffff5b 	bl	400970 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>
  400c08:	52800000 	mov	w0, #0x0                   	// #0
  400c0c:	f9400bf3 	ldr	x19, [sp, #16]
  400c10:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400c14:	d65f03c0 	ret

0000000000400c18 <_Z9sieve_stlv>:
  400c18:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400c1c:	910003fd 	mov	x29, sp
  400c20:	f9000bf3 	str	x19, [sp, #16]
  400c24:	d2978400 	mov	x0, #0xbc20                	// #48160
  400c28:	f2a017c0 	movk	x0, #0xbe, lsl #16
  400c2c:	97ffff55 	bl	400980 <_Znwm@plt>
  400c30:	aa0003f3 	mov	x19, x0
  400c34:	aa1303e0 	mov	x0, x19
  400c38:	940000e2 	bl	400fc0 <_ZNSt6bitsetILm100000000EEC1Ev>
  400c3c:	f90017b3 	str	x19, [x29, #40]
  400c40:	f94017a0 	ldr	x0, [x29, #40]
  400c44:	940000e7 	bl	400fe0 <_ZNSt6bitsetILm100000000EE3setEv>
  400c48:	529c1fc0 	mov	w0, #0xe0fe                	// #57598
  400c4c:	72a0bea0 	movk	w0, #0x5f5, lsl #16
  400c50:	b9003fa0 	str	w0, [x29, #60]
  400c54:	52800040 	mov	w0, #0x2                   	// #2
  400c58:	b9003ba0 	str	w0, [x29, #56]
  400c5c:	b9403ba1 	ldr	w1, [x29, #56]
  400c60:	5284e200 	mov	w0, #0x2710                	// #10000
  400c64:	6b00003f 	cmp	w1, w0
  400c68:	5400064c 	b.gt	400d30 <_Z9sieve_stlv+0x118>
  400c6c:	b9803ba0 	ldrsw	x0, [x29, #56]
  400c70:	aa0003e1 	mov	x1, x0
  400c74:	f94017a0 	ldr	x0, [x29, #40]
  400c78:	940000e4 	bl	401008 <_ZNKSt6bitsetILm100000000EE4testEm>
  400c7c:	12001c00 	and	w0, w0, #0xff
  400c80:	7100001f 	cmp	w0, #0x0
  400c84:	540004e0 	b.eq	400d20 <_Z9sieve_stlv+0x108>  // b.none
  400c88:	b9403ba1 	ldr	w1, [x29, #56]
  400c8c:	b9403ba0 	ldr	w0, [x29, #56]
  400c90:	1b007c20 	mul	w0, w1, w0
  400c94:	b90037a0 	str	w0, [x29, #52]
  400c98:	b98037b3 	ldrsw	x19, [x29, #52]
  400c9c:	f94017a0 	ldr	x0, [x29, #40]
  400ca0:	940000ea 	bl	401048 <_ZNKSt6bitsetILm100000000EE4sizeEv>
  400ca4:	eb00027f 	cmp	x19, x0
  400ca8:	1a9f27e0 	cset	w0, cc  // cc = lo, ul, last
  400cac:	12001c00 	and	w0, w0, #0xff
  400cb0:	7100001f 	cmp	w0, #0x0
  400cb4:	54000360 	b.eq	400d20 <_Z9sieve_stlv+0x108>  // b.none
  400cb8:	b98037a0 	ldrsw	x0, [x29, #52]
  400cbc:	aa0003e1 	mov	x1, x0
  400cc0:	f94017a0 	ldr	x0, [x29, #40]
  400cc4:	940000d1 	bl	401008 <_ZNKSt6bitsetILm100000000EE4testEm>
  400cc8:	12001c00 	and	w0, w0, #0xff
  400ccc:	7100001f 	cmp	w0, #0x0
  400cd0:	54000100 	b.eq	400cf0 <_Z9sieve_stlv+0xd8>  // b.none
  400cd4:	b9403fa0 	ldr	w0, [x29, #60]
  400cd8:	51000401 	sub	w1, w0, #0x1
  400cdc:	b9003fa1 	str	w1, [x29, #60]
  400ce0:	7100001f 	cmp	w0, #0x0
  400ce4:	54000060 	b.eq	400cf0 <_Z9sieve_stlv+0xd8>  // b.none
  400ce8:	52800020 	mov	w0, #0x1                   	// #1
  400cec:	14000002 	b	400cf4 <_Z9sieve_stlv+0xdc>
  400cf0:	52800000 	mov	w0, #0x0                   	// #0
  400cf4:	7100001f 	cmp	w0, #0x0
  400cf8:	540000a0 	b.eq	400d0c <_Z9sieve_stlv+0xf4>  // b.none
  400cfc:	b98037a0 	ldrsw	x0, [x29, #52]
  400d00:	aa0003e1 	mov	x1, x0
  400d04:	f94017a0 	ldr	x0, [x29, #40]
  400d08:	940000d6 	bl	401060 <_ZNSt6bitsetILm100000000EE5resetEm>
  400d0c:	b94037a1 	ldr	w1, [x29, #52]
  400d10:	b9403ba0 	ldr	w0, [x29, #56]
  400d14:	0b000020 	add	w0, w1, w0
  400d18:	b90037a0 	str	w0, [x29, #52]
  400d1c:	17ffffdf 	b	400c98 <_Z9sieve_stlv+0x80>
  400d20:	b9403ba0 	ldr	w0, [x29, #56]
  400d24:	11000400 	add	w0, w0, #0x1
  400d28:	b9003ba0 	str	w0, [x29, #56]
  400d2c:	17ffffcc 	b	400c5c <_Z9sieve_stlv+0x44>
  400d30:	f94017a0 	ldr	x0, [x29, #40]
  400d34:	f100001f 	cmp	x0, #0x0
  400d38:	54000060 	b.eq	400d44 <_Z9sieve_stlv+0x12c>  // b.none
  400d3c:	f94017a0 	ldr	x0, [x29, #40]
  400d40:	97ffff18 	bl	4009a0 <_ZdaPv@plt>
  400d44:	b9403fa0 	ldr	w0, [x29, #60]
  400d48:	f9400bf3 	ldr	x19, [sp, #16]
  400d4c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400d50:	d65f03c0 	ret

0000000000400d54 <_Z5sievev>:
  400d54:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400d58:	910003fd 	mov	x29, sp
  400d5c:	d2978400 	mov	x0, #0xbc20                	// #48160
  400d60:	f2a017c0 	movk	x0, #0xbe, lsl #16
  400d64:	97ffff1b 	bl	4009d0 <malloc@plt>
  400d68:	f9000fa0 	str	x0, [x29, #24]
  400d6c:	d2978402 	mov	x2, #0xbc20                	// #48160
  400d70:	f2a017c2 	movk	x2, #0xbe, lsl #16
  400d74:	12800001 	mov	w1, #0xffffffff            	// #-1
  400d78:	f9400fa0 	ldr	x0, [x29, #24]
  400d7c:	97fffef1 	bl	400940 <memset@plt>
  400d80:	529c1fc0 	mov	w0, #0xe0fe                	// #57598
  400d84:	72a0bea0 	movk	w0, #0x5f5, lsl #16
  400d88:	b9002fa0 	str	w0, [x29, #44]
  400d8c:	52800040 	mov	w0, #0x2                   	// #2
  400d90:	b9002ba0 	str	w0, [x29, #40]
  400d94:	b9402ba1 	ldr	w1, [x29, #40]
  400d98:	5284e200 	mov	w0, #0x2710                	// #10000
  400d9c:	6b00003f 	cmp	w1, w0
  400da0:	54000bec 	b.gt	400f1c <_Z5sievev+0x1c8>
  400da4:	b9402ba0 	ldr	w0, [x29, #40]
  400da8:	11007c01 	add	w1, w0, #0x1f
  400dac:	7100001f 	cmp	w0, #0x0
  400db0:	1a80b020 	csel	w0, w1, w0, lt  // lt = tstop
  400db4:	13057c00 	asr	w0, w0, #5
  400db8:	93407c00 	sxtw	x0, w0
  400dbc:	d37ef400 	lsl	x0, x0, #2
  400dc0:	f9400fa1 	ldr	x1, [x29, #24]
  400dc4:	8b000020 	add	x0, x1, x0
  400dc8:	b9400001 	ldr	w1, [x0]
  400dcc:	b9402ba0 	ldr	w0, [x29, #40]
  400dd0:	6b0003e2 	negs	w2, w0
  400dd4:	12001000 	and	w0, w0, #0x1f
  400dd8:	12001042 	and	w2, w2, #0x1f
  400ddc:	5a824400 	csneg	w0, w0, w2, mi  // mi = first
  400de0:	52800022 	mov	w2, #0x1                   	// #1
  400de4:	1ac02040 	lsl	w0, w2, w0
  400de8:	0a000020 	and	w0, w1, w0
  400dec:	7100001f 	cmp	w0, #0x0
  400df0:	540008e0 	b.eq	400f0c <_Z5sievev+0x1b8>  // b.none
  400df4:	b9402ba1 	ldr	w1, [x29, #40]
  400df8:	b9402ba0 	ldr	w0, [x29, #40]
  400dfc:	1b007c20 	mul	w0, w1, w0
  400e00:	b90027a0 	str	w0, [x29, #36]
  400e04:	b94027a1 	ldr	w1, [x29, #36]
  400e08:	529c1fe0 	mov	w0, #0xe0ff                	// #57599
  400e0c:	72a0bea0 	movk	w0, #0x5f5, lsl #16
  400e10:	6b00003f 	cmp	w1, w0
  400e14:	540007cc 	b.gt	400f0c <_Z5sievev+0x1b8>
  400e18:	b94027a0 	ldr	w0, [x29, #36]
  400e1c:	11007c01 	add	w1, w0, #0x1f
  400e20:	7100001f 	cmp	w0, #0x0
  400e24:	1a80b020 	csel	w0, w1, w0, lt  // lt = tstop
  400e28:	13057c00 	asr	w0, w0, #5
  400e2c:	93407c00 	sxtw	x0, w0
  400e30:	d37ef400 	lsl	x0, x0, #2
  400e34:	f9400fa1 	ldr	x1, [x29, #24]
  400e38:	8b000020 	add	x0, x1, x0
  400e3c:	b9400001 	ldr	w1, [x0]
  400e40:	b94027a0 	ldr	w0, [x29, #36]
  400e44:	6b0003e2 	negs	w2, w0
  400e48:	12001000 	and	w0, w0, #0x1f
  400e4c:	12001042 	and	w2, w2, #0x1f
  400e50:	5a824400 	csneg	w0, w0, w2, mi  // mi = first
  400e54:	52800022 	mov	w2, #0x1                   	// #1
  400e58:	1ac02040 	lsl	w0, w2, w0
  400e5c:	0a000020 	and	w0, w1, w0
  400e60:	7100001f 	cmp	w0, #0x0
  400e64:	54000100 	b.eq	400e84 <_Z5sievev+0x130>  // b.none
  400e68:	b9402fa0 	ldr	w0, [x29, #44]
  400e6c:	51000401 	sub	w1, w0, #0x1
  400e70:	b9002fa1 	str	w1, [x29, #44]
  400e74:	7100001f 	cmp	w0, #0x0
  400e78:	54000060 	b.eq	400e84 <_Z5sievev+0x130>  // b.none
  400e7c:	52800020 	mov	w0, #0x1                   	// #1
  400e80:	14000002 	b	400e88 <_Z5sievev+0x134>
  400e84:	52800000 	mov	w0, #0x0                   	// #0
  400e88:	7100001f 	cmp	w0, #0x0
  400e8c:	54000360 	b.eq	400ef8 <_Z5sievev+0x1a4>  // b.none
  400e90:	b94027a0 	ldr	w0, [x29, #36]
  400e94:	11007c01 	add	w1, w0, #0x1f
  400e98:	7100001f 	cmp	w0, #0x0
  400e9c:	1a80b020 	csel	w0, w1, w0, lt  // lt = tstop
  400ea0:	13057c00 	asr	w0, w0, #5
  400ea4:	2a0003e4 	mov	w4, w0
  400ea8:	93407c80 	sxtw	x0, w4
  400eac:	d37ef400 	lsl	x0, x0, #2
  400eb0:	f9400fa1 	ldr	x1, [x29, #24]
  400eb4:	8b000020 	add	x0, x1, x0
  400eb8:	b9400001 	ldr	w1, [x0]
  400ebc:	b94027a0 	ldr	w0, [x29, #36]
  400ec0:	6b0003e2 	negs	w2, w0
  400ec4:	12001000 	and	w0, w0, #0x1f
  400ec8:	12001042 	and	w2, w2, #0x1f
  400ecc:	5a824400 	csneg	w0, w0, w2, mi  // mi = first
  400ed0:	52800022 	mov	w2, #0x1                   	// #1
  400ed4:	1ac02040 	lsl	w0, w2, w0
  400ed8:	2a2003e0 	mvn	w0, w0
  400edc:	2a0003e3 	mov	w3, w0
  400ee0:	93407c80 	sxtw	x0, w4
  400ee4:	d37ef400 	lsl	x0, x0, #2
  400ee8:	f9400fa2 	ldr	x2, [x29, #24]
  400eec:	8b000040 	add	x0, x2, x0
  400ef0:	0a030021 	and	w1, w1, w3
  400ef4:	b9000001 	str	w1, [x0]
  400ef8:	b94027a1 	ldr	w1, [x29, #36]
  400efc:	b9402ba0 	ldr	w0, [x29, #40]
  400f00:	0b000020 	add	w0, w1, w0
  400f04:	b90027a0 	str	w0, [x29, #36]
  400f08:	17ffffbf 	b	400e04 <_Z5sievev+0xb0>
  400f0c:	b9402ba0 	ldr	w0, [x29, #40]
  400f10:	11000400 	add	w0, w0, #0x1
  400f14:	b9002ba0 	str	w0, [x29, #40]
  400f18:	17ffff9f 	b	400d94 <_Z5sievev+0x40>
  400f1c:	f9400fa0 	ldr	x0, [x29, #24]
  400f20:	97fffe84 	bl	400930 <free@plt>
  400f24:	b9402fa0 	ldr	w0, [x29, #44]
  400f28:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400f2c:	d65f03c0 	ret

0000000000400f30 <_Z41__static_initialization_and_destruction_0ii>:
  400f30:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400f34:	910003fd 	mov	x29, sp
  400f38:	b9001fa0 	str	w0, [x29, #28]
  400f3c:	b9001ba1 	str	w1, [x29, #24]
  400f40:	b9401fa0 	ldr	w0, [x29, #28]
  400f44:	7100041f 	cmp	w0, #0x1
  400f48:	540001e1 	b.ne	400f84 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400f4c:	b9401ba1 	ldr	w1, [x29, #24]
  400f50:	529fffe0 	mov	w0, #0xffff                	// #65535
  400f54:	6b00003f 	cmp	w1, w0
  400f58:	54000161 	b.ne	400f84 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400f5c:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400f60:	9106a000 	add	x0, x0, #0x1a8
  400f64:	97fffe97 	bl	4009c0 <_ZNSt8ios_base4InitC1Ev@plt>
  400f68:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400f6c:	91022002 	add	x2, x0, #0x88
  400f70:	d0000080 	adrp	x0, 412000 <free@GLIBC_2.17>
  400f74:	9106a001 	add	x1, x0, #0x1a8
  400f78:	90000000 	adrp	x0, 400000 <_init-0x8f0>
  400f7c:	91288000 	add	x0, x0, #0xa20
  400f80:	97fffe84 	bl	400990 <__cxa_atexit@plt>
  400f84:	d503201f 	nop
  400f88:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400f8c:	d65f03c0 	ret

0000000000400f90 <_GLOBAL__sub_I_main>:
  400f90:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400f94:	910003fd 	mov	x29, sp
  400f98:	529fffe1 	mov	w1, #0xffff                	// #65535
  400f9c:	52800020 	mov	w0, #0x1                   	// #1
  400fa0:	97ffffe4 	bl	400f30 <_Z41__static_initialization_and_destruction_0ii>
  400fa4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400fa8:	d65f03c0 	ret

0000000000400fac <_ZNSt9_SanitizeILm0EE14_S_do_sanitizeEm>:
  400fac:	d10043ff 	sub	sp, sp, #0x10
  400fb0:	f90007e0 	str	x0, [sp, #8]
  400fb4:	d503201f 	nop
  400fb8:	910043ff 	add	sp, sp, #0x10
  400fbc:	d65f03c0 	ret

0000000000400fc0 <_ZNSt6bitsetILm100000000EEC1Ev>:
  400fc0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400fc4:	910003fd 	mov	x29, sp
  400fc8:	f9000fa0 	str	x0, [x29, #24]
  400fcc:	f9400fa0 	ldr	x0, [x29, #24]
  400fd0:	94000033 	bl	40109c <_ZNSt12_Base_bitsetILm1562500EEC1Ev>
  400fd4:	d503201f 	nop
  400fd8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400fdc:	d65f03c0 	ret

0000000000400fe0 <_ZNSt6bitsetILm100000000EE3setEv>:
  400fe0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400fe4:	910003fd 	mov	x29, sp
  400fe8:	f9000fa0 	str	x0, [x29, #24]
  400fec:	f9400fa0 	ldr	x0, [x29, #24]
  400ff0:	94000039 	bl	4010d4 <_ZNSt12_Base_bitsetILm1562500EE9_M_do_setEv>
  400ff4:	f9400fa0 	ldr	x0, [x29, #24]
  400ff8:	9400004a 	bl	401120 <_ZNSt6bitsetILm100000000EE14_M_do_sanitizeEv>
  400ffc:	f9400fa0 	ldr	x0, [x29, #24]
  401000:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401004:	d65f03c0 	ret

0000000000401008 <_ZNKSt6bitsetILm100000000EE4testEm>:
  401008:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40100c:	910003fd 	mov	x29, sp
  401010:	f9000fa0 	str	x0, [x29, #24]
  401014:	f9000ba1 	str	x1, [x29, #16]
  401018:	90000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  40101c:	910f0000 	add	x0, x0, #0x3c0
  401020:	aa0003e2 	mov	x2, x0
  401024:	f9400ba1 	ldr	x1, [x29, #16]
  401028:	f9400fa0 	ldr	x0, [x29, #24]
  40102c:	94000047 	bl	401148 <_ZNKSt6bitsetILm100000000EE8_M_checkEmPKc>
  401030:	f9400ba1 	ldr	x1, [x29, #16]
  401034:	f9400fa0 	ldr	x0, [x29, #24]
  401038:	94000063 	bl	4011c4 <_ZNKSt6bitsetILm100000000EE15_Unchecked_testEm>
  40103c:	12001c00 	and	w0, w0, #0xff
  401040:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401044:	d65f03c0 	ret

0000000000401048 <_ZNKSt6bitsetILm100000000EE4sizeEv>:
  401048:	d10043ff 	sub	sp, sp, #0x10
  40104c:	f90007e0 	str	x0, [sp, #8]
  401050:	d29c2000 	mov	x0, #0xe100                	// #57600
  401054:	f2a0bea0 	movk	x0, #0x5f5, lsl #16
  401058:	910043ff 	add	sp, sp, #0x10
  40105c:	d65f03c0 	ret

0000000000401060 <_ZNSt6bitsetILm100000000EE5resetEm>:
  401060:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  401064:	910003fd 	mov	x29, sp
  401068:	f9000fa0 	str	x0, [x29, #24]
  40106c:	f9000ba1 	str	x1, [x29, #16]
  401070:	90000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  401074:	910f4000 	add	x0, x0, #0x3d0
  401078:	aa0003e2 	mov	x2, x0
  40107c:	f9400ba1 	ldr	x1, [x29, #16]
  401080:	f9400fa0 	ldr	x0, [x29, #24]
  401084:	94000031 	bl	401148 <_ZNKSt6bitsetILm100000000EE8_M_checkEmPKc>
  401088:	f9400ba1 	ldr	x1, [x29, #16]
  40108c:	f9400fa0 	ldr	x0, [x29, #24]
  401090:	9400005f 	bl	40120c <_ZNSt6bitsetILm100000000EE16_Unchecked_resetEm>
  401094:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401098:	d65f03c0 	ret

000000000040109c <_ZNSt12_Base_bitsetILm1562500EEC1Ev>:
  40109c:	d10043ff 	sub	sp, sp, #0x10
  4010a0:	f90007e0 	str	x0, [sp, #8]
  4010a4:	f94007e1 	ldr	x1, [sp, #8]
  4010a8:	d29af060 	mov	x0, #0xd783                	// #55171
  4010ac:	f2a002e0 	movk	x0, #0x17, lsl #16
  4010b0:	f100001f 	cmp	x0, #0x0
  4010b4:	540000ab 	b.lt	4010c8 <_ZNSt12_Base_bitsetILm1562500EEC1Ev+0x2c>  // b.tstop
  4010b8:	f900003f 	str	xzr, [x1]
  4010bc:	91002021 	add	x1, x1, #0x8
  4010c0:	d1000400 	sub	x0, x0, #0x1
  4010c4:	17fffffb 	b	4010b0 <_ZNSt12_Base_bitsetILm1562500EEC1Ev+0x14>
  4010c8:	d503201f 	nop
  4010cc:	910043ff 	add	sp, sp, #0x10
  4010d0:	d65f03c0 	ret

00000000004010d4 <_ZNSt12_Base_bitsetILm1562500EE9_M_do_setEv>:
  4010d4:	d10083ff 	sub	sp, sp, #0x20
  4010d8:	f90007e0 	str	x0, [sp, #8]
  4010dc:	f9000fff 	str	xzr, [sp, #24]
  4010e0:	f9400fe1 	ldr	x1, [sp, #24]
  4010e4:	d29af060 	mov	x0, #0xd783                	// #55171
  4010e8:	f2a002e0 	movk	x0, #0x17, lsl #16
  4010ec:	eb00003f 	cmp	x1, x0
  4010f0:	54000128 	b.hi	401114 <_ZNSt12_Base_bitsetILm1562500EE9_M_do_setEv+0x40>  // b.pmore
  4010f4:	f94007e0 	ldr	x0, [sp, #8]
  4010f8:	f9400fe1 	ldr	x1, [sp, #24]
  4010fc:	92800002 	mov	x2, #0xffffffffffffffff    	// #-1
  401100:	f8217802 	str	x2, [x0, x1, lsl #3]
  401104:	f9400fe0 	ldr	x0, [sp, #24]
  401108:	91000400 	add	x0, x0, #0x1
  40110c:	f9000fe0 	str	x0, [sp, #24]
  401110:	17fffff4 	b	4010e0 <_ZNSt12_Base_bitsetILm1562500EE9_M_do_setEv+0xc>
  401114:	d503201f 	nop
  401118:	910083ff 	add	sp, sp, #0x20
  40111c:	d65f03c0 	ret

0000000000401120 <_ZNSt6bitsetILm100000000EE14_M_do_sanitizeEv>:
  401120:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  401124:	910003fd 	mov	x29, sp
  401128:	f9000fa0 	str	x0, [x29, #24]
  40112c:	f9400fa0 	ldr	x0, [x29, #24]
  401130:	94000049 	bl	401254 <_ZNSt12_Base_bitsetILm1562500EE9_M_hiwordEv>
  401134:	f9400000 	ldr	x0, [x0]
  401138:	97ffff9d 	bl	400fac <_ZNSt9_SanitizeILm0EE14_S_do_sanitizeEm>
  40113c:	d503201f 	nop
  401140:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401144:	d65f03c0 	ret

0000000000401148 <_ZNKSt6bitsetILm100000000EE8_M_checkEmPKc>:
  401148:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40114c:	910003fd 	mov	x29, sp
  401150:	f90017a0 	str	x0, [x29, #40]
  401154:	f90013a1 	str	x1, [x29, #32]
  401158:	f9000fa2 	str	x2, [x29, #24]
  40115c:	f94013a1 	ldr	x1, [x29, #32]
  401160:	d29c1fe0 	mov	x0, #0xe0ff                	// #57599
  401164:	f2a0bea0 	movk	x0, #0x5f5, lsl #16
  401168:	eb00003f 	cmp	x1, x0
  40116c:	54000109 	b.ls	40118c <_ZNKSt6bitsetILm100000000EE8_M_checkEmPKc+0x44>  // b.plast
  401170:	90000000 	adrp	x0, 401000 <_ZNSt6bitsetILm100000000EE3setEv+0x20>
  401174:	910f8000 	add	x0, x0, #0x3e0
  401178:	d29c2003 	mov	x3, #0xe100                	// #57600
  40117c:	f2a0bea3 	movk	x3, #0x5f5, lsl #16
  401180:	f94013a2 	ldr	x2, [x29, #32]
  401184:	f9400fa1 	ldr	x1, [x29, #24]
  401188:	97fffe0a 	bl	4009b0 <_ZSt24__throw_out_of_range_fmtPKcz@plt>
  40118c:	d503201f 	nop
  401190:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401194:	d65f03c0 	ret

0000000000401198 <_ZNKSt12_Base_bitsetILm1562500EE10_M_getwordEm>:
  401198:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40119c:	910003fd 	mov	x29, sp
  4011a0:	f9000fa0 	str	x0, [x29, #24]
  4011a4:	f9000ba1 	str	x1, [x29, #16]
  4011a8:	f9400ba0 	ldr	x0, [x29, #16]
  4011ac:	94000042 	bl	4012b4 <_ZNSt12_Base_bitsetILm1562500EE12_S_whichwordEm>
  4011b0:	aa0003e1 	mov	x1, x0
  4011b4:	f9400fa0 	ldr	x0, [x29, #24]
  4011b8:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  4011bc:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4011c0:	d65f03c0 	ret

00000000004011c4 <_ZNKSt6bitsetILm100000000EE15_Unchecked_testEm>:
  4011c4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4011c8:	910003fd 	mov	x29, sp
  4011cc:	f9000bf3 	str	x19, [sp, #16]
  4011d0:	f90017a0 	str	x0, [x29, #40]
  4011d4:	f90013a1 	str	x1, [x29, #32]
  4011d8:	f94017a0 	ldr	x0, [x29, #40]
  4011dc:	f94013a1 	ldr	x1, [x29, #32]
  4011e0:	97ffffee 	bl	401198 <_ZNKSt12_Base_bitsetILm1562500EE10_M_getwordEm>
  4011e4:	aa0003f3 	mov	x19, x0
  4011e8:	f94013a0 	ldr	x0, [x29, #32]
  4011ec:	94000028 	bl	40128c <_ZNSt12_Base_bitsetILm1562500EE10_S_maskbitEm>
  4011f0:	8a000260 	and	x0, x19, x0
  4011f4:	f100001f 	cmp	x0, #0x0
  4011f8:	1a9f07e0 	cset	w0, ne  // ne = any
  4011fc:	12001c00 	and	w0, w0, #0xff
  401200:	f9400bf3 	ldr	x19, [sp, #16]
  401204:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401208:	d65f03c0 	ret

000000000040120c <_ZNSt6bitsetILm100000000EE16_Unchecked_resetEm>:
  40120c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401210:	910003fd 	mov	x29, sp
  401214:	f9000bf3 	str	x19, [sp, #16]
  401218:	f90017a0 	str	x0, [x29, #40]
  40121c:	f90013a1 	str	x1, [x29, #32]
  401220:	f94013a0 	ldr	x0, [x29, #32]
  401224:	9400001a 	bl	40128c <_ZNSt12_Base_bitsetILm1562500EE10_S_maskbitEm>
  401228:	aa2003f3 	mvn	x19, x0
  40122c:	f94017a0 	ldr	x0, [x29, #40]
  401230:	f94013a1 	ldr	x1, [x29, #32]
  401234:	94000026 	bl	4012cc <_ZNSt12_Base_bitsetILm1562500EE10_M_getwordEm>
  401238:	f9400001 	ldr	x1, [x0]
  40123c:	8a010261 	and	x1, x19, x1
  401240:	f9000001 	str	x1, [x0]
  401244:	f94017a0 	ldr	x0, [x29, #40]
  401248:	f9400bf3 	ldr	x19, [sp, #16]
  40124c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401250:	d65f03c0 	ret

0000000000401254 <_ZNSt12_Base_bitsetILm1562500EE9_M_hiwordEv>:
  401254:	d10043ff 	sub	sp, sp, #0x10
  401258:	f90007e0 	str	x0, [sp, #8]
  40125c:	f94007e1 	ldr	x1, [sp, #8]
  401260:	d2978300 	mov	x0, #0xbc18                	// #48152
  401264:	f2a017c0 	movk	x0, #0xbe, lsl #16
  401268:	8b000020 	add	x0, x1, x0
  40126c:	910043ff 	add	sp, sp, #0x10
  401270:	d65f03c0 	ret

0000000000401274 <_ZNSt12_Base_bitsetILm1562500EE11_S_whichbitEm>:
  401274:	d10043ff 	sub	sp, sp, #0x10
  401278:	f90007e0 	str	x0, [sp, #8]
  40127c:	f94007e0 	ldr	x0, [sp, #8]
  401280:	92401400 	and	x0, x0, #0x3f
  401284:	910043ff 	add	sp, sp, #0x10
  401288:	d65f03c0 	ret

000000000040128c <_ZNSt12_Base_bitsetILm1562500EE10_S_maskbitEm>:
  40128c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  401290:	910003fd 	mov	x29, sp
  401294:	f9000fa0 	str	x0, [x29, #24]
  401298:	f9400fa0 	ldr	x0, [x29, #24]
  40129c:	97fffff6 	bl	401274 <_ZNSt12_Base_bitsetILm1562500EE11_S_whichbitEm>
  4012a0:	2a0003e1 	mov	w1, w0
  4012a4:	d2800020 	mov	x0, #0x1                   	// #1
  4012a8:	9ac12000 	lsl	x0, x0, x1
  4012ac:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4012b0:	d65f03c0 	ret

00000000004012b4 <_ZNSt12_Base_bitsetILm1562500EE12_S_whichwordEm>:
  4012b4:	d10043ff 	sub	sp, sp, #0x10
  4012b8:	f90007e0 	str	x0, [sp, #8]
  4012bc:	f94007e0 	ldr	x0, [sp, #8]
  4012c0:	d346fc00 	lsr	x0, x0, #6
  4012c4:	910043ff 	add	sp, sp, #0x10
  4012c8:	d65f03c0 	ret

00000000004012cc <_ZNSt12_Base_bitsetILm1562500EE10_M_getwordEm>:
  4012cc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4012d0:	910003fd 	mov	x29, sp
  4012d4:	f9000fa0 	str	x0, [x29, #24]
  4012d8:	f9000ba1 	str	x1, [x29, #16]
  4012dc:	f9400ba0 	ldr	x0, [x29, #16]
  4012e0:	97fffff5 	bl	4012b4 <_ZNSt12_Base_bitsetILm1562500EE12_S_whichwordEm>
  4012e4:	d37df000 	lsl	x0, x0, #3
  4012e8:	f9400fa1 	ldr	x1, [x29, #24]
  4012ec:	8b000020 	add	x0, x1, x0
  4012f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4012f4:	d65f03c0 	ret

00000000004012f8 <__libc_csu_init>:
  4012f8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4012fc:	910003fd 	mov	x29, sp
  401300:	a901d7f4 	stp	x20, x21, [sp, #24]
  401304:	90000094 	adrp	x20, 411000 <__FRAME_END__+0xf7e8>
  401308:	90000095 	adrp	x21, 411000 <__FRAME_END__+0xf7e8>
  40130c:	9136c294 	add	x20, x20, #0xdb0
  401310:	913682b5 	add	x21, x21, #0xda0
  401314:	a902dff6 	stp	x22, x23, [sp, #40]
  401318:	cb150294 	sub	x20, x20, x21
  40131c:	f9001ff8 	str	x24, [sp, #56]
  401320:	2a0003f6 	mov	w22, w0
  401324:	aa0103f7 	mov	x23, x1
  401328:	9343fe94 	asr	x20, x20, #3
  40132c:	aa0203f8 	mov	x24, x2
  401330:	97fffd70 	bl	4008f0 <_init>
  401334:	b4000194 	cbz	x20, 401364 <__libc_csu_init+0x6c>
  401338:	f9000bb3 	str	x19, [x29, #16]
  40133c:	d2800013 	mov	x19, #0x0                   	// #0
  401340:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  401344:	aa1803e2 	mov	x2, x24
  401348:	aa1703e1 	mov	x1, x23
  40134c:	2a1603e0 	mov	w0, w22
  401350:	91000673 	add	x19, x19, #0x1
  401354:	d63f0060 	blr	x3
  401358:	eb13029f 	cmp	x20, x19
  40135c:	54ffff21 	b.ne	401340 <__libc_csu_init+0x48>  // b.any
  401360:	f9400bb3 	ldr	x19, [x29, #16]
  401364:	a941d7f4 	ldp	x20, x21, [sp, #24]
  401368:	a942dff6 	ldp	x22, x23, [sp, #40]
  40136c:	f9401ff8 	ldr	x24, [sp, #56]
  401370:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401374:	d65f03c0 	ret

0000000000401378 <__libc_csu_fini>:
  401378:	d65f03c0 	ret

Disassembly of section .fini:

000000000040137c <_fini>:
  40137c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401380:	910003fd 	mov	x29, sp
  401384:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401388:	d65f03c0 	ret
